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| 1. general description the pcf85134 is a peripheral device which interfaces to almost any liquid crystal display (lcd) 1 with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 60 segments. it can be easily cascaded for larger lcd applications. the pcf85134 is compatible with most microcontrollers and communicates via the two-line bidirectional i 2 c-bus. communication overheads are minimized by a display ram with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes). for a selection of nxp lcd segment drivers, see table 26 on page 45 . 2. features and benefits ? single-chip lcd controller and driver ? selectable backplane drive configurations : static, 2, 3, or 4 backplane multiplexing ? 60 segment outputs allowing to drive: ? 30 7-segment alphanumeric characters ? 15 14-segment alphanumeric characters ? any graphics of up to 240 elements ? cascading supported for larger applications ? 60 ? 4-bit display data storage ram ? wide lcd supply range: from 2.5 v for low threshold lcds up to 6.5 v for high threshold twisted nematic lcds ? internal lcd bias generation with voltage follower buffers ? selectable display bias configurations: static, 1 2 , or 1 3 ? wide logic power supply range: from 1.8 v to 5.5 v ? lcd and logic supplies may be separated ? low power consumption ? 400 khz i 2 c-bus interface ? no external components required ? display memory bank switching in static and duplex drive mode ? versatile blinking modes ? silicon gate cmos process pcf85134 universal 60 x 4 lcd segment driv er for multiple x rates up to 1:4 rev. 3 ? 12 may 2014 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 20 .
pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 2 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 3. ordering information 3.1 ordering options 4. marking table 1. ordering information type number package name description version PCF85134HL lqfp80 plastic low profile quad flat package; 80 leads; body 12 ? 12 ? 1.4 mm sot315-1 table 2. ordering options product type number orderable part number sales item (12nc) delivery form ic revision PCF85134HL/1 PCF85134HL/1,118 935290742118 tape and reel, 13 inch 1 table 3. marking codes type number marking code PCF85134HL/1 PCF85134HL pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 3 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 5. block diagram fig 1. block diagram of pcf85134 d d d / & ' 9 2 / 7 $ * ( 6 ( / ( & 7 2 5 & / 2 & . 6 ( / ( & 7 $ 1 ' 7 , 0 , 1 * % / , 1 . ( 5 7 , 0 ( % $ 6 ( 2 6 & , / / $ 7 2 5 , 1 3 8 7 ) , / 7 ( 5 6 , & % 8 6 & 2 1 7 5 2 / / ( 5 3 2 : ( 5 2 1 5 ( 6 ( 7 & / . 6 < 1 & 2 6 & 6 & / 6 ' $ % $ & . 3 / $ 1 ( 2 8 7 3 8 7 6 ' , 6 3 / $ < & 2 1 7 5 2 / % 3 % 3 % 3 % 3 ' , 6 3 / $ < 6 ( * 0 ( 1 7 2 8 7 3 8 7 6 ' , 6 3 / $ < 5 ( * , 6 7 ( 5 2 8 7 3 8 7 % $ 1 . 6 ( / ( & 7 $ 1 ' % / , 1 . & 2 1 7 5 2 / 6 w r 6 6 $ 9 ' ' $ $ $ 3 & ) / & ' % , $ 6 * ( 1 ( 5 $ 7 2 5 9 6 6 9 / & ' & 2 0 0 $ 1 ' ' ( & 2 ' ( : 5 , 7 ( ' $ 7 $ & 2 1 7 5 2 / ' , 6 3 / $ < 5 $ 0 ' $ 7 $ 3 2 , 1 7 ( 5 $ 1 ' $ 8 7 2 , 1 & 5 ( 0 ( 1 7 6 8 % $ ' ' 5 ( 6 6 & 2 8 1 7 ( 5 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 4 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 6. pinning information 6.1 pinning top view. for mechanical details, see figure 24 . fig 2. pin configuration for sot315-1 (pcf85134) 3 & ) 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 9 / & ' 6 9 6 6 6 6 $ 6 $ 6 $ 6 $ 6 2 6 & 6 6 < 1 & 6 9 ' ' 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 % 3 6 % 3 6 % 3 6 % 3 6 q f 6 q f 6 q f 6 q f 6 6 ' $ 6 6 & / 6 & / . 6 d d d pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 5 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 6.2 pin description table 4. pin description input or input/output pins must always be at a defined level (v ss or v dd ) unless otherwise specified. symbol pin type description s31 to s59 1 to 29 output lcd segment output 31 to 59 bp0 to bp3 30 to 33 output lcd backplane output 0 to 3 n.c. 34 to 37 - not connected; do not connect and do not use as feed through sda 38 input/output i 2 c-bus serial data input and output scl 39 input i 2 c-bus serial clock input clk 40 input/output external clock input and internal clock output v dd 41 supply supply voltage sync 42 input/output cascade synchronization input and output (active low) osc 43 input enable input for internal oscillator a0 to a2 44 to 46 input subaddress counter input 0 to 2 sa0 47 input i 2 c-bus slave address input 0 v ss 48 supply ground supply voltage v lcd 49 supply input of lcd supply voltage s0 to s30 50 to 80 output lcd segment output 0 to 30 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 6 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 7. functional description the pcf85134 is a versatile peripheral de vice designed to interface between any microcontroller to a wide variety of lcd segment or dot matrix displays (see figure 3 ). it can directly drive any static or multiplexed l cd containing up to four backplanes and up to 60 segments. the display configurations possible with the pcf85134 depend on the required number of active backplane outputs. a selection of display configurations is given in ta b l e 5 . all of the display configurations given in ta b l e 5 can be implemented in a typical system as shown in figure 4 . [1] 7-segment display has eight el ements including the decimal point. [2] 14-segment display has 16 elements in cluding decimal point and accent dot. fig 3. example of displays suitable for pcf85134 table 5. selection of possi ble display configurations number of backplanes icons digits/characters dot matrix/ elements 7-segment [1] 14-segment [2] 4 240 30 15 240 (4 ? 60) 3 180 22 11 180 (3 ? 60) 2 120 15 7 120 (2 ? 60) 16 0736 0 ( 1 ? 60) v h j p h q w z l w k g r w v h j p h q w z l w k g r w d q g d f f h q w d d d g r w p d w u l [ pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 7 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates the host microcontroller maintains the 2-line i 2 c-bus communication channel with the pcf85134. biasing voltages for the multiplexed lcd wa veforms are generated internally, removing the need for an external bias generator. the internal oscillator is selected by connecting pin osc to v ss . the only other connections required to complete the system are the power supplies (pins v dd , v ss , and v lcd ) and the lcd panel selected for the application. 7.1 power-on reset (por) at power-on the pcf85134 resets to the following starting conditions: ? all backplane and segment outputs are set to v lcd ? the selected drive mode is: 1:4 multiplex with 1 3 bias ? blinking is switched off ? input and output bank selectors are reset ? the i 2 c-bus interface is initialized ? the data pointer and the subaddress counter are cleared (set to logic 0) ? the display is disabled (bit e = 0, see ta b l e 1 2 ) remark: do not transfer data on the i 2 c-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between v lcd and v ss . if the 1 2 bias voltage level for the 1:2 multiplex drive mode configurati on is selected, the center impedance is bypassed by switch. the lcd voltage can be temperature compensated externally, using the supply to pin v lcd . fig 4. typical system configuration + 2 6 7 0 , & 5 2 & 2 1 7 5 2 / / ( 5 5 ? w u & e 6 ' $ 6 & / v h j p h q w g u l y h v e d f n s o d q h v / & ' 3 $ 1 ( / x s w r h o h p h q w v 3 & ) 9 ' ' 9 6 6 9 6 6 d d d 9 / & ' 9 / & ' 9 ' ' $ $ 6 $ $ 2 6 & pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 8 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 7.3 lcd voltage selector the lcd voltage selector coordinates the mult iplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by the mode-set command from the command decoder. the biasing configurations that apply to the preferred modes of operatio n, together with the biasing characteristics as functions of v lcd and the resulting discrimina tion ratios (d) are given in ta b l e 6 . discrimination is a term which is defined as the ratio of the on and off rms voltage across a segment. it can be thought of as a measurement of contrast. a practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th(off) ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode, a suitable choice is v lcd >3v th(off) . multiplex drive modes of 1:3 and 1:4 with 1 2 bias are possible but the discrimination and hence the contrast ratios are smaller. bias is calculated by , where the values for a are a = 1 for 1 2 bias a = 2 for 1 3 bias the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 1 : (1) where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode the rms off-state voltage (v off(rms) ) for the lcd is calculated with equation 2 : (2) discrimination is the ratio of v on(rms) to v off(rms) and is determined from equation 3 : table 6. biasing characteristics lcd drive mode number of: lcd bias configuration backplanes levels static 1 2 static 0 1 ? 1:2 multiplex 2 3 1 2 0.354 0.791 2.236 1:2 multiplex 2 4 1 3 0.333 0.745 2.236 1:3 multiplex 3 4 1 3 0.333 0.638 1.915 1:4 multiplex 4 4 1 3 0.333 0.577 1.732 v off rms ?? ------------------------ - v on rms ?? ----------------------- - d v on rms ?? off rms ?? ------------------------ - = 1 1a + ------------ - v on rms ?? a 2 2a n ++ n 1a + ?? ? ----------------------------- - v lcd = v off rms ?? a 2 2a ? n + n 1a + ?? ? ----------------------------- - v lcd = pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 9 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates (3) using equation 3 , the discrimination for an lcd drive mode of 1:3 multiplex with 1 2 bias is and the discrimination for an lcd drive mode of 1:4 multiplex with 1 2 bias is . the advantage of these lcd drive modes is a reduction of the lcd full scale voltage v lcd as follows: ? 1:3 multiplex ( 1 2 bias): ? 1:4 multiplex ( 1 2 bias): these compare with when 1 3 bias is used. v lcd is sometimes referred as the lcd operating voltage. 7.3.1 electro-optical performance suitable values for v on(rms) and v off(rms) are dependent on the lcd liquid used. the rms voltage, at which a pixel is switched on or off, determines the transmissibility of the pixel. for any given liquid, there are two threshold values defined. one point is at 10 % relative transmission (at v th(off) ) and the other at 90 % relative transmission (at v th(on) ), see figure 5 . for a good contrast performance, the following rules should be followed: (4) (5) v on(rms) and v off(rms) are properties of the display driver and are affected by the selection of a, n (see equation 1 to equation 3 ) and the v lcd voltage. v th(off) and v th(on) are properties of the lcd liquid and can be provided by the module manufacturer. v th(off) is sometimes just named v th . v th(on) is sometimes named saturation voltage v sat . it is important to match the module properties to those of the driver in order to achieve optimum performance. d v on rms ?? v off rms ?? ---------------------- - a 2 2a n ++ a 2 2a ? n + --------------------------- == 3 1.732 = 21 3 ---------- 1.528 = v lcd 6v off rms ?? ? 2.449v off rms ?? == v lcd 43 ? ?? 3 --------------------- - 2.309v off rms ?? == v lcd 3v off rms ?? = v on rms ?? ?? ? ?? ?? ? pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 10 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates fig 5. electro-optical characteristic: relative transmission curve of the liquid 9 5 0 6 > 9 @ 2 ) ) 6 ( * 0 ( 1 7 * 5 ( < 6 ( * 0 ( 1 7 2 1 6 ( * 0 ( 1 7 9 w k r i i 9 w k r q 5 h o d w l y h 7 u d q v p l v v l r q d d d pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 11 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 7.4 lcd drive mode waveforms 7.4.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. backplane and segment drive waveforms for this mode are shown in figure 6 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = v lcd . v state2 (t) = v (sn + 1) (t) ? v bp0 (t). v off(rms) = 0 v. fig 6. static driv e mode waveforms d d d 9 6 6 9 / & ' 9 6 6 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' v w d w h 9 % 3 6 q 6 q v w d w h 9 d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h r q v w d w h r i i 7 i u pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 12 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 7.4.2 1:2 multiplex drive mode when two backplanes are provided in the lcd, the 1:2 multiplex mode applies. the pcf85134 allows the use of 1 2 bias or 1 3 bias in this mode as shown in figure 7 and figure 8 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.791v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.354v lcd . fig 7. waveforms for the 1:2 multiplex drive mode with 1 2 bias d d d v w d w h % 3 d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h % 3 v w d w h v w d w h 9 6 6 9 / & ' 9 / & ' 9 6 6 9 6 6 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 6 q 6 q 7 i u pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 13 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.745v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 8. waveforms for the 1:2 multiplex drive mode with 1 3 bias d d d v w d w h % 3 d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h % 3 v w d w h v w d w h 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 6 q 6 q 7 i u 9 6 6 9 / & ' 9 / & ' 9 / & ' pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 14 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 7.4.3 1:3 multiplex drive mode when three backplanes are provided in the lcd, the 1:3 multiplex drive mode applies, as shown in figure 9 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.638v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 9. waveforms for the 1:3 multiplex drive mode with 1 3 bias d d d v w d w h % 3 e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h % 3 v w d w h v w d w h d : d y h i r u p v d w g u l y h u % 3 6 q 6 q 6 q 7 i u 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 15 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 7.4.4 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies, as shown in figure 10 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.577v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 10. waveforms for the 1:4 multiplex drive mode with 1 3 bias d d d v w d w h % 3 e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h % 3 v w d w h v w d w h % 3 d : d y h i r u p v d w g u l y h u % 3 6 q 6 q 6 q 6 q 7 i u 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 16 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 7.5 oscillator the internal logic and the lcd drive signals of the pcf85134 are timed by the frequency f clk . it equals either the built -in oscillator frequency f osc or the external clock frequency f clk(ext) . the clock frequency f clk determines the lcd frame frequency (f fr ). 7.5.1 internal clock the internal oscillator is enable d by connecting pin osc to pin v ss . in this case, the output from pin clk is the clock signal for any cascaded pcf85134 in the system. 7.5.2 external clock pin clk is enabled as an external clock input by connecting pin osc to v dd . remark: a clock signal must always be supplied to the device. removing the clock may freeze the lcd in a dc state, which is not suitable for the liquid crystal. 7.6 timing and frame frequency the pcf85134 timing controls the internal da ta flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the correct timing relationship between each pcf85134 in the system is maintained by the synchronization signal at pin sync . the timing also generates the lcd frame signal whose frequency is derived from the clock frequency. the frame signal frequency is a fixed division of the clock frequency from either the internal or an external clock. 7.7 display register the display register holds the display data while the corresponding multiplex signals are generated. 7.8 segment outputs the lcd drive section includes 60 segment outputs (s0 to s59) which should be connected directly to the lcd. the segment output signals are generated based on the multiplexed backpla ne signals and with data resident in the display register. when less than 60 segment outputs are required, the unused segment outputs must be left open-circuit. table 7. lcd frame frequencies operating mode ratio frame frequency with respect to f clk (typical) unit f clk =1970hz 82 hz f fr f clk 24 ------- - = pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 17 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 7.9 backplane outputs the lcd drive section includes four backplane outputs bp0 to bp3 which must be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. ? in 1:4 multiplex drive mode: bp0 to bp3 must be connected directly to the lcd. if less than four backplane outputs are required, the unused outputs can be left open-circuit. ? in 1:3 multiplex drive mode bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. ? in 1:2 multiplex drive mode bp0 and bp2, respectively, bp1 and bp3 carry the same signals and can also be paired to increase the drive capabilities. ? in static drive mode, the same signal is ca rried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 display ram the display ram is a static 60 ? 4-bit ram which stores lcd data. a logic 1 in the ram bit map indicates the on-state (v on(rms) ) of the corresponding lcd element. similarly, a logic 0 indicates the off-state (v off(rms) ). for more information on v on(rms) and v off(rms) , see section 7.3 . there is a one-to-one correspondence between ? the bits in the ram bitmap and the lcd elements ? the ram columns and the segment outputs ? the ram rows and the backplane outputs. the display ram bit map, figure 11 , shows row 0 to row 3 which correspond with the backplane outputs bp0 to bp3, and column 0 to column 59 which correspond with the segment outputs s0 to s59. in multiplexed lcd applications, the data of each row of the display ram is time-multiplexed with the corresponding backplane (row 0 with bp0, row 1 with bp1, and so on). the display ram bit map shows the direct re lationship between the display ram addresses and the segment outputs and between the bits in a ram word and the backplane outputs. fig 11. display ram bit map g l v s o d \ 5 $ 0 d g g u h v v h v v h j p h q w r x w s x w v 6 g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v % 3 d d d f r o x p q v u r z v xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 18 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates x = data bit unchanged. fig 12. relationship between lcd layout, drive mode, display ram filling order and display data transmitted over the i 2 c-bus d d m d f e ' 3 i h j g 0 6 % / 6 % e ' 3 f d g j i h 0 6 % / 6 % d e i j h f g ' 3 0 6 % / 6 % f e d i j h g ' 3 0 6 % / 6 % g u l y h p r g h v w d w l f p x o w l s o h [ p x o w l s o h [ p x o w l s o h [ / & ' v h j p h q w v / & ' e d f n s o d q h v g l v s o d \ 5 $ 0 i l o o l q j r u g h u w u d q v p l w w h g g l v s o d \ e \ w h % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 q f [ [ [ e [ [ [ d [ [ [ i [ [ [ j [ [ [ h [ [ [ g [ [ [ ' 3 [ [ [ q q q q q q q u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v % 3 e \ w h f r o x p q v g l v s o d \ 5 $ 0 d g g u h v v v h j p h q w r x w s x w v v q d e [ [ i j [ [ h f [ [ g ' 3 [ [ q q q e \ w h e \ w h u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v % 3 f r o x p q v g l v s o d \ 5 $ 0 d g g u h v v v h j p h q w r x w s x w v v q e ' 3 f [ d g j [ i h [ [ q q e \ w h e \ w h e \ w h u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v % 3 f r o x p q v g l v s o d \ 5 $ 0 d g g u h v v v h j p h q w r x w s x w v v q q d f e ' 3 i h j g e \ w h e \ w h e \ w h e \ w h e \ w h u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v % 3 f r o x p q v g l v s o d \ 5 $ 0 d g g u h v v v h j p h q w r x w s x w v v 6 q 6 q 6 q 6 q ' 3 d i e j h f g 6 q 6 q 6 q 6 q 6 q 6 q 6 q 6 q ' 3 d i e j h f g 6 q 6 q 6 q ' 3 d i e j h f g 6 q 6 q ' 3 d i e j h f g pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 19 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates when display data is transmitted to the pcf8 5134, the display bytes received are stored in the display ram in accordan ce with the selected lcd multip lex drive mode. the data is stored as it arrives and depending on the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples. to illustrate th e filling order, an example of a 7-segment display showing all drive modes is given in figure 12 . the ram filling organization depicted applies equally to other lcd types. the following applies to figure 12 : ? in static drive mode the eight transmitted data bits are placed into row 0 as one byte. ? in 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and row 1 as four successive 2-bit ram words. ? in 1:3 multiplex drive mode the eight bits are placed in triples into row 0, row 1, and row 2 as three successive 3-bit ram words, with bit 3 of the third address left unchanged. it is not recommended to use this bit in a display because of the difficult addressing. this last bit may, if necessary, be controlled by an additional transfer to this address. but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted (see section 7.10.3 ). ? in 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples into row 0, row 1, row 2, and row 3 as two successive 4-bit ram words. 7.10.1 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequen ce commences with the initialization of the data pointer by the load-data-pointer command (see ta b l e 11 ). following this command, an arriving data byte is stored at the displa y ram address indicated by the data pointer. the filling order is shown in figure 12 . after each byte is stored , the content of the data pointer is automatically incremented by a value dependent on the selected lcd drive mode: ? in static drive mode by eight. ? in 1:2 multiplex drive mode by four. ? in 1:3 multiplex drive mode by three. ? in 1:4 multiplex drive mode by two. if an i 2 c-bus data access terminates early, then the state of the data pointer is unknown. consequently, the data pointer must be rewritten before further ram accesses. 7.10.2 subaddress counter the storage of display data is determined by the content of the subaddress counter. storage is allowed only when the content of the subaddress counter matches with the hardware subaddress applied to a0, a1, and a2. the subaddress counter value is defined by the device-select command (see table 14 ). if the content of the subaddress counter and the hardware subaddress do not match, th en data storage is inhibited but the data pointer is incremented as if data storage ha d taken place. the subaddress counter is also incremented when the data pointer overflows. pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 20 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates in cascaded applications each pcf85134 in the cascade must be addressed separately. initially, the first pcf85134 is selected by sending the device-select command matching the first hardware subaddress. then the data pointer is set to the preferred display ram address by sending the load-data-pointer command. once the display ram of the first pcf85134 has been written, the second pcf85134 is selected by sending the device-select comma nd again. this time however the command matches the hardware subaddress of the second device. next the load-data-pointer command is sent to select the preferred display ram address of the second pcf85134. this last step is very important because during writing data to the first pcf85134, the data pointer of the second pcf85134 is incremen ted. in addition, the hardware subaddress should not be changed while the device is being accessed on the i 2 c-bus interface. 7.10.3 ram writing in 1:3 multiplex drive mode in 1:3 multiplex drive mode, t he ram is written as shown in ta b l e 8 (see figure 12 as well). if the bit at position bp2/s2 would be writ ten by a second byte tr ansmitted, then the mapping of the segment bits would cha nge as illustrated in ta b l e 9 . in the case described in ta b l e 9 the ram has to be written entirely and bp2/s2, bp2/s5, bp2/s8, and so on, have to be connected to elements on the display. this can be achieved by a combination of writing and rewriting the ram like follows: ? in the first write to the ram, bits a7 to a0 are written. ? in the second write, bits b7 to b0 are writt en, overwriting bits a1 and a0 with bits b7 and b6. ? in the third write, bits c7 to c0 are writte n, overwriting bits b1 and b0 with bits c7 and c6. table 8. standard ram filling in 1:3 multiplex drive mode assumption: bp2/s2, bp2/s5, bp2/s8 etc. are not connected to any elements on the display. display ram bits (rows)/ backplane outputs (bpn) display ram addresses (columns)/segment outputs (sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 : 1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 : 2 a5 a2 - b5 b2 - c5 c2 - d5 : 3 ----------: table 9. entire ram filling by rewriting in 1:3 multiplex drive mode assumption: bp2/s2, bp2/s5, bp2/s8 etc. are connected to elements on the display. display ram bits (rows)/ backplane outputs (bpn) display ram addresses (columns)/segment outputs (sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 : 1 a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 : 2 a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 : 3 ----------: pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 21 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates depending on the method of wr iting to the ram (standard or entire filling by rewriting), some elements remain unused or can be used. but it has to be considered in the module layout process as well as in the driver software design. 7.10.4 bank selector 7.10.4.1 output bank selector the output bank selector (see ta b l e 1 5 ) selects one of the four rows per display ram address for transfer to the display register. the actual row selected depends on the particular lcd drive mode in operation and on the instant in the multiplex sequence. ? in 1:4 multiplex mode, all ram addresses of row 0 are selected, these are followed by the contents of row 1, 2, and then 3 ? in 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially ? in 1:2 multiplex mode, rows 0 and 1 are selected ? in static mode, row 0 is selected the sync signal resets these sequences to the following starting points: ? row 3 for 1:4 multiplex ? row 2 for 1:3 multiplex ? row 1 for 1:2 multiplex ? row 0 for static mode the pcf85134 includes a ram bank switching fe ature in the static and 1:2 multiplex drive modes. in the static drive mode, the bank-s elect command may request the contents of row 2 to be selected for display instead of the contents of row 0. in the 1:2 multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. this gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 7.10.4.2 input bank selector the input bank selector loads display data into the display data in accordance with the selected lcd drive configuration. display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see ta b l e 1 5 ). the input bank selector functions inde pendently to the output bank selector. 7.11 blinking the display blinking capabilitie s of the pcf85134 are very versatile. the whole display can blink at frequencie s selected by the blink-select command (see table 16 ). the blink frequencies are derived from the clock freque ncy. the ratio between the clock and blink frequency depends on the blink mode selected (see table 10 ). pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 22 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates an additional feature is for an arbitrary select ion of lcd segments to blink. this applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. with the output bank selector, the displayed ram banks are exchanged with alternate ram banks at the blink frequency. this mode can also be specified by the b link-select command. in the 1:3 and 1:4 multiplex modes, where no alternate ram bank is available, groups of lcd elements can blink by selectively changing the display ram data at fixed time intervals. the entire display can blink at a frequency other than the nominal blink frequency. this can be effectively performed by resetting and setting the display enable bit e at the required rate using the mode-set command (see ta b l e 1 2 ). 7.12 command decoder the command decoder identifies command bytes that arrive on the i 2 c-bus. there are five commands: table 10. blink frequencies blink mode operating mode ratio blink frequency with respect to f clk (typical) unit f clk = 1970 hz off - blinking off hz 12.5 hz 21.3 hz 30.6 hz f blink f clk 768 -------- - = f blink f clk 1536 ----------- - = f blink f clk 3072 ----------- - = table 11. definition of commands command operation code reference bit 7 6 5 4 3 2 1 0 mode-set 1 1 0 0 e b m[1:0] ta b l e 1 2 load-data-pointer 0 p[6:0] ta b l e 1 3 device-select 1 1 1 0 0 a[2:0] ta b l e 1 4 bank-select 1 1 1 1 1 0 i o ta b l e 1 5 blink-select 1 1 1 1 0 ab bf[1:0] ta b l e 1 6 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 23 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates [1] the possibility to disable the display allows implementation of blinking under external control. [2] default value. [3] the display is disabled by setting all backplane and segment outputs to v lcd . [4] not applicable for static drive mode. [1] default value. [1] default value. table 12. mode-set command bit description bit symbol value description 7 to 4 - 1100 fixed value 3e display status [1] 0 [2] disabled (blank) [3] 1 enable 2b lcd bias configuration [4] 0 [2] 1 3 bias 1 1 2 bias 1 to 0 m[1:0] lcd drive mode selection 01 static; one backplane 10 1:2 multiplex; two backplanes 11 1:3 multiplex; three backplanes 00 [2] 1:4 multiplex; four backplanes table 13. load-data-pointer command bit description see section 7.10.1 on page 19 . bit symbol value description 7 - 0 fixed value 6 to 0 p[6:0] 0000000 [1] to 0111011 7-bit binary value, 0 to 59; transferred to the data pointer to define one of 60 display ram addresses table 14. device-select command bit description see section 7.10.2 on page 19 . bit symbol value description 7 to 3 - 11100 fixed value 2 to 0 a[2:0] 000 [1] to 111 3-bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 24 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates [1] the bank-select command has no effect in 1:3 or 1:4 multiplex drive modes. [2] default value. [1] default value. [2] normal blinking is assumed when the lcd multiplex drive modes 1:3 or 1:4 are selected. [3] alternate ram bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. [4] for the blink frequencies, see table 10 . 7.13 display controller the display controller executes the commands identified by the command decoder. it contains the status registers of the pcf8513 4 and coordinates their effects. the display controller is also responsible for loading disp lay data into the display ram in the correct filling order. table 15. bank-select command bit description see section 7.10.4 on page 21 . bit symbol value description static 1:2 multiplex [1] 7 to 2 - 111110 fixed value 1i input bank selection : storage of arriving display data 0 [2] ram row 0 ram rows 0 and 1 1 ram row 2 ram rows 2 and 3 0o output bank selection : retrieval of lcd display data 0 [2] ram row 0 ram rows 0 and 1 1 ram row 2 ram rows 2 and 3 table 16. blink-select command bit description see section 7.11 on page 21 . bit symbol value description 7 to 3 - 11110 fixed value 2ab blink mode selection 0 [1] normal blinking [2] 1 alternate ram bank blinking [3] 1 to 0 bf[1:0] blink frequency selection [4] 00 [1] off 01 1 10 2 11 3 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 25 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 8. characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal . bit transfer is illustrated in figure 13 . 8.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low change of the data line, while the clock is high, is defined as the start condition (s). a low-to-high change of the data line, while the clock is high, is defined as the stop condition (p). the start and stop condit ions are illustrated in figure 14 . 8.2 system configuration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master; and the devices which are controlled by the master are the slaves. the system configuration is shown in figure 15 . fig 13. bit transfer p e d g d w d o l q h v w d e o h g d w d y d o l g f k d q j h r i g d w d d o o r z h g 6 ' $ 6 & / fig 14. definition of start and stop conditions p e f 6 ' $ 6 & / 3 6 7 2 3 f r q g l w l r q 6 ' $ 6 & / 6 6 7 $ 5 7 f r q g l w l r q pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 26 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 8.3 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is un limited. each byte of 8 bits is followed by an acknowledge cycle. ? a slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. ? a master receiver must generate an acknowle dge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be considered). ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is illustrated in figure 16 . fig 15. system configuration p j d 6 ' $ 6 & / 0 $ 6 7 ( 5 7 5 $ 1 6 0 , 7 7 ( 5 5 ( & ( , 9 ( 5 0 $ 6 7 ( 5 7 5 $ 1 6 0 , 7 7 ( 5 6 / $ 9 ( 7 5 $ 1 6 0 , 7 7 ( 5 5 ( & ( , 9 ( 5 6 / $ 9 ( 5 ( & ( , 9 ( 5 0 $ 6 7 ( 5 7 5 $ 1 6 0 , 7 7 ( 5 5 ( & ( , 9 ( 5 fig 16. acknowledgement of the i 2 c-bus p e f 6 6 7 $ 5 7 f r q g l w l r q f o r f n s x o v h i r u d f n q r z o h g j h p h q w q r w d f n q r z o h g j h d f n q r z o h g j h g d w d r x w s x w e \ w u d q v p l w w h u g d w d r x w s x w e \ u h f h l y h u 6 & / i u r p p d v w h u pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 27 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 8.4 i 2 c-bus controller the pcf85134 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the pcf85134 are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, on the transferre d command data and on the hardware subaddress. in single device applications, the hardw are subaddress inputs a0, a1, and a2 are normally tied to v ss which defines the hardware subaddress 0. in multiple device applications a0, a1, and a2 are tied to v ss or v dd using a binary coding scheme, so that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. 8.5 input filters to enhance noise immunity in electrically ad verse environments, rc low-pass filters are provided on the sda and scl lines. 8.6 i 2 c-bus protocol two i 2 c-bus slave addresses (0111 000 and 0111 001) are used to address the pcf85134. the entire i 2 c-bus slave address byte is shown in ta b l e 1 7 . the pcf85134 is a write-only device and does not respond to a read access, therefore bit 0 should always be logic 0. bit 1 of the slave address byte, that a pcf85134 will respond to, is defined by the level tied to its sa0 input (v ss for logic 0 and v dd for logic 1). having two reserved slave addresses allows the following on the same i 2 c-bus: ? up to 16 pcf85134 for ve ry large lcd applications ? the use of two types of lcd multiplex drive the i 2 c-bus protocol is shown in figure 17 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of the available pcf85134 slave addresses. all pcf85134 with the same sa0 level acknowledg e in parallel to the slave address. all pcf85134 with the alternative sa0 level ignore the whole i 2 c-bus transfer. table 17. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb 011100sa0r/w pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 28 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates after acknowledgement, the control byte is sent defining if the next byte is a ram or command information. the control byte also de fines if the next byte is a control byte or further ram or command data (see figure 18 and ta b l e 1 8 ). in this way, it is possible to configure the device an d then fill the display ram with little overhead. the command bytes and control bytes are also acknowledged by all addressed pcf85134 connected to the bus. the display bytes are stored in the display ram at the address specified by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated. fig 17. i 2 c-bus protocol ( ; $ 0 3 / ( 6 d w u d q v p l w w z r e \ w h v r i 5 $ 0 g d w d p j o 6 $ 6 f r q w u r o e \ w h v o d y h d g g u h v v 5 $ 0 f r p p d q g e \ w h 5 $ 0 ' $ 7 $ 0 6 % / 6 % $ $ 3 5 : 6 $ 6 $ $ $ 3 5 $ 0 ' $ 7 $ $ e w u d q v p l w w z r f r p p d q g e \ w h v & 2 0 0 $ 1 ' 6 $ 6 $ $ $ 3 & 2 0 0 $ 1 ' $ $ f w u d q v p l w r q h f r p p d q g e \ w h d q g w z r 5 $ 0 g d w h e \ w h v & 2 0 0 $ 1 ' 6 $ 6 $ $ $ 3 5 $ 0 ' $ 7 $ $ 5 $ 0 ' $ 7 $ $ $ & 2 5 6 fig 18. control byte format table 18. control byte description bit symbol value description 7co continue bit 0 last control byte 1 control bytes continue 6rs register selection 0 command register 1 data register 5 to 0 - unused p j o q r w u h o h y d q w & 2 5 6 0 6 % / 6 % pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 29 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates the acknowledgement, after each byte, is made only by the a0, a1, and a2 addressed pcf85134. after the last display byte, the i 2 c-bus master issues a stop condition (p). alternatively a start may be issued to restart i 2 c-bus access. 9. internal circuitry fig 19. device protection diagram 6 $ 9 ' ' 9 ' ' 9 6 6 9 6 6 9 / & ' 9 6 6 6 ' $ d d k 9 6 6 6 & / 9 6 6 & / . 9 ' ' 9 6 6 2 6 & 9 ' ' 9 6 6 6 < 1 & 9 ' ' 9 6 6 $ $ $ 9 ' ' 9 6 6 % 3 % 3 % 3 % 3 9 / & ' 9 6 6 6 w r 6 9 / & ' 9 6 6 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 30 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 10. safety notes caution this device is sensitive to electrostatic di scharge (esd). observe precautions for handling electrostatic sensitive devices. such precautions are described in the ansi/esd s20.20 , iec/st 61340-5 , jesd625-a or equivalent standards. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to av oid such artifacts, v lcd and v dd must be applied or removed together. pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 31 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 11. limiting values [1] stresses above these values listed may cause permanent damage to the device. [2] pins sda, scl, clk, sync , sa0, osc, and a0 to a2. [3] pins s0 to s59 and bp0 to bp3. [4] pass level; human body model (hbm), according to ref. 8 ? jesd22-a114 ? . [5] pass level; charged-device model (cdm), according to ref. 9 ? jesd22-c101 ? . [6] pass level; latch-up testing according to ref. 10 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [7] according to the store and transport requirements (see ref. 13 ? um10569 ? ) the devices have to be stored at a temperature of +8 ? c to +45 ? c and a humidity of 25 % to 75 %. table 19. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v i dd supply current ? 50 +50 ma v lcd lcd supply voltage ? 0.5 +7.5 v i dd(lcd) lcd supply current ? 50 +50 ma i ss ground supply current ? 50 +50 ma v i input voltage [2] ? 0.5 +6.5 v i i input current [2] ? 10 +10 ma v o output voltage [2] ? 0.5 +6.5 v [3] ? 0.5 +7.5 v i o output current [2] [3] ? 10 +10 ma p tot total power dissipation - 400 mw p/out power dissipation per output -1 0 0m w v esd electrostatic discharge voltage hbm [4] - ? 2500 v cdm [5] - ? 1000 v i lu latch-up current v lu =11.5v [6] -2 0 0m a t stg storage temperature [7] ? 65 +150 ?c t amb ambient temperature operating device ? 40 +85 ?c pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 32 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 12. static characteristics table 20. static characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 1.8 - 5.5 v v lcd lcd supply voltage 2.5 - 6.5 v i dd supply current f clk(ext) = 1536 hz [1] -82 0 ? a i dd(lcd) lcd supply current f clk(ext) = 1536 hz [1] -2 46 0 ? a logic v i input voltage v ss ? 0.5 - v dd + 0.5 v v il low-level input voltage on pins clk, sync , osc, a0 to a2 and sa0 v ss -0 . 3 v dd v v ih high-level input voltage on pins clk, sync , osc, a0 to a2 and sa0 0.7v dd -v dd v v por power-on reset voltage 1.01.31.6v i ol low-level output current output sink current; v ol = 0.4 v; v dd = 5 v; on pins clk and sync 1- - ma i oh high-level output current output source current; v oh = 4.6 v; v dd = 5 v; on pin clk 1- - ma i l leakage current v i = v dd or v ss ; on pins sa0, a0 to a2 and clk ? 1- +1 ? a v i = v dd ; on pin osc ? 1- +1 ? a c i input capacitance [2] --7p f i 2 c-bus; pins sda and scl [3] v i input voltage v ss ? 0.5 - 5.5 v v il low-level input voltage pin scl v ss -0 . 3 v dd v pin sda v ss -0 . 2 v dd v v ih high-level input voltage 0.7v dd -5 . 5v i ol low-level output current output sink current; v ol = 0.4 v; v dd = 5 v; on pin sda 3- - ma i l leakage current v i = v dd or v ss ? 1- +1 ? a c i input capacitance [2] --7p f lcd outputs output pins bp0 to bp3 v bp voltage on pin bp c bpl = 35 nf [4] ? 100 - +100 mv r bp resistance on pin bp v lcd = 5 v [5] -1 . 51 0k ? output pins s0 to s59 v s voltage on pin s c sgm = 35 nf [6] ? 100 - +100 mv r s resistance on pin s v lcd = 5 v [5] -6 . 01 3 . 5k ? pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 33 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates [1] lcd outputs are open-circuit; inputs at v ss or v dd ; external clock with 50 % duty factor; i 2 c-bus inactive. [2] not tested, design specification only. [3] the i 2 c-bus interface of pcf85134 is 5 v tolerant. [4] c bpl = backplane capacitance. [5] measured on sample basis only. [6] c sgm = segment capacitance. pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 34 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 13. dynamic characteristics table 21. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit clock internal: output pin clk f osc oscillator frequency v dd = 5 v [1] 1440 1970 2640 hz external: input pin clk f clk(ext) external clock frequency v dd = 5 v 800 - 3600 hz t clk(h) high-level clock time 130 - - ? s t clk(l) low-level clock time 130 - - ? s synchronization: input pin sync t pd(sync_n) sync propagation delay -30-ns t sync_nl sync low time 1 - - ? s outputs: pins bp0 to bp3 and s0 to s59 t pd(drv) driver propagation delay v lcd = 5 v - - 30 ? s i 2 c-bus: timing [2] pin scl f scl scl frequency - - 400 khz t low low period of the scl clock 1.3 - - ? s t high high period of the scl clock 0.6 - - ? s pin sda t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns pins scl and sda t buf bus free time between a stop and start condition 1.3 - - ? s t su;sto set-up time for stop condition 0.6 - - ? s t hd;sta hold time (repeated) start condition 0.6 - - ? s t su;sta set-up time for a repeated start condition 0.6 - - ? s t r rise time of both sda and scl signals --0.3 ? s pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 35 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates [1] typical output (duty cycle ? = 50 %). [2] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . t f fall time of both sda and scl signals --0.3 ? s c b capacitive load for each bus line --400pf t w(spike) spike pulse width - - 50 ns table 21. dynamic characteristics ?continued v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 6.5 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit fig 20. driver timing waveforms d d k 9 ' ' 9 ' ' 9 ' ' 9 ' ' i f o n w 3 ' 6 < 1 & b 1 w 3 ' 6 < 1 & b 1 w f o n + w f o n / 6 < 1 & & / . 9 9 w 3 ' g u y % 3 w r % 3 d q g 6 w r 6 w 6 < 1 & b 1 / 9 ' ' 9 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 36 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates fig 21. i 2 c-bus timing waveforms 6 ' $ p j d 6 ' $ 6 & / w 6 8 6 7 $ w 6 8 6 7 2 w + ' 6 7 $ w % 8 ) w / 2 : w + ' ' $ 7 w + , * + w u w i w 6 8 ' $ 7 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 37 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 14. application information 14.1 cascaded operation large display configurations of up to 16 pcf85134s can be recognized on the same i 2 c-bus by using the 3-bit hardware subaddress (a0, a1 and a2) and the programmable i 2 c-bus slave address (sa0). when cascaded pcf85134 are synchronized, they can share the backplane signals from one of the devices in the cascade. such an arrangement is cost-effective in large lcd applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. th e other pcf85134 of the cascade contribute additional segment outputs. the backplanes c an either be connected together to enhance the drive capability or some can be left open -circuit (such as the ones from the slave in figure 22 ) or just some of the master and some of the slave will be taken to facilitate the layout of the display. table 22. addressing cascaded pcf85134 cluster bit sa0 pin a2 pin a1 pin a0 device 100000 0011 0102 0113 1004 1015 1106 1117 210008 0019 01010 01111 10012 10113 11014 11115 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 38 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates the sync line is provided to maintain the corr ect synchronization between all cascaded pcf85134. synchronization is guaranteed after a power-on reset. the only time that sync is likely to be needed is if synchronization is accidentally lost (for example, by noise in adverse electrical environments or by defi ning a multiplex drive mode when pcf85134 with different sa0 levels are cascaded). sync is organized as an input/output pin. the output selection is realized as an open-drain driver with an internal pull-up resistor. a pcf85134 asserts the sync line at the onset of its last active backplane signal and monitors the sync line at all other times. if synchronization in the cascade is lost, it is restored by the first pcf85134 to assert sync . the timing relationship between the backplane waveforms and the sync signal for the various drive modes of the pcf85134 are shown in figure 23 . the contact resistance between the sync on each cascaded devi ce must be controlled. if the resistance is too high, the device is no t able to synchronize properly; this is applicable to chip-on-glass applications. the maximum sync contact resistance allowed for the number of devices in cascade is given in table 23 . (1) is master (osc connected to v ss ). (2) is slave (osc connected to v dd ). fig 22. cascaded pcf85134 configuration + 2 6 7 0 , & 5 2 3 5 2 & ( 6 6 2 5 0 , & 5 2 & 2 1 7 5 2 / / ( 5 6 ' $ 6 & / & / . 2 6 & 6 < 1 & v h j p h q w g u l y h v e d f n s o d q h v v h j p h q w g u l y h v / & ' 3 $ 1 ( / 3 & ) $ $ $ 6 $ 9 6 6 9 6 6 9 6 6 9 ' ' 9 ' ' 9 / & ' 9 / & ' 9 ' ' 9 / & ' d d d 6 ' $ 6 & / 6 < 1 & & / . 2 6 & % 3 w r % 3 r s h q f l u f x l w $ $ $ 6 $ 3 & ) % 3 w r % 3 5 w u & e ? pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 39 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates the pcf85134 can always be cascaded with other devices of the same type or conditionally with other devices of the same fa mily. this allows opti mal drive selection for a given number of pixels to display. figure 21 and figure 23 show the timing of the synchronization signals. only one master but mu ltiple slaves are allowed in a ca scade. all devices in the cascade have to use the same clock whether it is supplied externally or provided by the master. table 23. sync contact resistance number of devices maximum contact resistance 2 6000 ? 3 to 5 2200 ? 6 to 10 1200 ? 11 to 16 700 ? fig 23. synchronization of the cascade for various pcf85134 drive modes 7 i u i i u % 3 6 < 1 & % 3 e l d v 6 < 1 & % 3 e l d v d v w d w l f g u l y h p r g h e p x o w l s o h [ g u l y h p r g h f p x o w l s o h [ g u l y h p r g h g p x o w l s o h [ g u l y h p r g h % 3 e l d v 6 < 1 & 6 < 1 & % 3 e l d v p j o pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 40 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates if an external clock source is used, all pcf85134 in the cascade must be configured such as to receive the clock from that exte rnal source (pin osc connected to v dd ). it must be ensured that the clock tree is designed such that on all pcf85134 the clock propagation delay from the clock sour ce to all pcf85134 in the cascade is as equal as possible since otherwise synchronization artifacts may occur. in mixed cascading configurations , care has to be taken that the specifications of the individual cascaded devices are met at all times. pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 41 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 15. package outline fig 24. package outline sot315-1 (lqfp80) 8 1 , 7 $ p d [ $ $ $ e s f ( h + ( / / s = \ z y 5 ( ) ( 5 ( 1 & ( 6 2 8 7 / , 1 ( 9 ( 5 6 , 2 1 ( 8 5 2 3 ( $ 1 3 5 2 - ( & 7 , 2 1 , 6 6 8 ( ' $ 7 ( , ( & - ( ' ( & - ( , 7 $ p p r r ' , 0 ( 1 6 , 2 1 6 p p d u h w k h r u l j l q d o g l p h q v l r q v 1 r w h 3 o d v w l f r u p h w d o s u r w u x v l r q v r i p p p d [ l p x p s h u v l g h d u h q r w l q f o x g h g 6 2 7 ( 0 6 ' + ' ( = ' e s h ( $ $ / s g h w d l o ; / $ % f ' + e s ( + $ y 0 % ' = ' $ = ( h y 0 $ ; \ s l q l q g h [ z 0 z 0 p p v f d o h / 4 ) 3 s o d v w l f o r z s u r i l o h t x d g i o d w s d f n d j h o h d g v e r g \ [ [ p p 6 2 7 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 42 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 16. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. 17. packing information for tape and reel packing information, please see ref. 12 ? sot315-1_118 ? on page 48 . 18. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 18.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 43 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates ? inspection and repair ? lead-free soldering versus snpb soldering 18.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 18.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 25 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 4 and 25 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 25 . table 24. snpb eutectic process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 25. lead-free process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 44 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 25. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 45 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 19. appendix 19.1 lcd segment driver selection table 26. selection of lcd segment drivers type name number of elements at mux v dd (v) v lcd (v) f fr (hz) v lcd (v) charge pump v lcd (v) temperature compensat. t amb ( ?c) interface package aec- q100 1:1 1:2 1:3 1:4 1:6 1:8 1:9 pca8553dtt 40 80 120 160 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256 [1] nn ? 40 to 105 i 2 c / spi tssop56 y pca8546att - - - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 95 i 2 c tssop56 y pca8546btt - - - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 95 spi tssop56 y pca8547aht 44 88 - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 95 i 2 ctqfp64y pca8547bht 44 88 - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 95 spi tqfp64 y PCF85134HL 60 120 180 240 - - - 1.8 to 5.5 2.5 to 6.5 82 n n ? 40 to 85 i 2 clqfp80n pca85134h 60 120 180 240 - - - 1.8 to 5.5 2.5 to 8 82 n n ? 40 to 95 i 2 clqfp80y pca8543ahl 60 120 - 240 - - - 2.5 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 105 i 2 clqfp80y pcf8545att - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300 [1] nn ? 40 to 85 i 2 c tssop56 n pcf8545btt - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300 [1] nn ? 40 to 85 spi tssop56 n pcf8536at - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 85 i 2 c tssop56 n pcf8536bt - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 85 spi tssop56 n pca8536at - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 95 i 2 c tssop56 y pca8536bt - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 95 spi tssop56 y pcf8537ah 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 85 i 2 ctqfp64n pcf8537bh 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 85 spi tqfp64 n pca8537ah 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 95 i 2 ctqfp64y pca8537bh 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 95 spi tqfp64 y pca9620h 60 120 - 240 320 480 - 2.5 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 105 i 2 clqfp80y pca9620u 60 120 - 240 320 480 - 2.5 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 105 i 2 c bare die y pcf8576du 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 n n ? 40 to 85 i 2 c bare die n pcf8576eug 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 n n ? 40 to 85 i 2 c bare die n pca8576fug 40 80 120 160 - - - 1.8 to 5.5 2.5 to 8 200 n n ? 40 to 105 i 2 c bare die y pcf85133u 80 160 240 320 - - - 1.8 to 5.5 2.5 to 6.5 82, 110 [2] nn ? 40 to 85 i 2 c bare die n pca85133u 80 160 240 320 - - - 1.8 to 5.5 2.5 to 8 82, 110 [2] nn ? 40 to 95 i 2 c bare die y xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 46 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates [1] software programmable. [2] hardware selectable. pca85233ug 80 160 240 320 - - - 1.8 to 5.5 2.5 to 8 150, 220 [2] nn ? 40 to 105 i 2 c bare die y pcf85132u 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 60 to 90 [1] nn ? 40 to 85 i 2 c bare die n pca8530dug 102 204 - 408 - - - 2.5 to 5.5 4 to 12 45 to 300 [1] yy ? 40 to 105 i 2 c / spi bare die y pca85132u 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 60 to 90 [1] nn ? 40 to 95 i 2 c bare die y pca85232u 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 117 to 176 [1] nn ? 40 to 95 i 2 c bare die y pcf8538ug 102 204 - 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300 [1] yy ? 40 to 85 i 2 c / spi bare die n pca8538ug 102 204 - 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300 [1] yy ? 40 to 105 i 2 c / spi bare die y table 26. selection of lcd segment drivers ?continued type name number of elements at mux v dd (v) v lcd (v) f fr (hz) v lcd (v) charge pump v lcd (v) temperature compensat. t amb ( ?c) interface package aec- q100 1:1 1:2 1:3 1:4 1:6 1:8 1:9 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 47 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 20. abbreviations table 27. abbreviations acronym description cdm charged-device model cmos complementary metal-oxide semiconductor dc direct current emc electromagnetic compatibility esd electrostatic discharge hbm human body model i 2 c inter-integrated circuit bus ic integrated circuit lcd liquid crystal display lsb least significant bit mos metal-oxide semiconductor msb most significant bit msl moisture sensitivity level por power-on reset rc resistance-capacitance ram random access memory rms root mean square rtc real-time clock scl serial clock line sda serial data line smd surface-mount device pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 48 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 21. references [1] an10365 ? surface mount reflow soldering description [2] an10853 ? esd and emc sensitivity of ic [3] an11267 ? emc and system level esd design guidelines for lcd drivers [4] an11494 ? cascading nxp lcd segment drivers [5] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [6] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [7] ipc/jedec j-std-020d ? moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices [8] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [9] jesd22-c101 ? field-induced charged-device model test method for electrostatic-discharge-withstand thresh olds of microelectronic components [10] jesd78 ? ic latch-up test [11] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [12] sot315-1_118 ? lqfp80; reel pack; smd, 13", packing information [13] um10569 ? store and transport requirements [14] um10204 ? i 2 c-bus specification and user manual 22. revision history table 28. revision history document id release date data sheet status change notice supersedes pcf85134 v.3 20140512 product data sheet - pcf85134 v.2 modifications: ? improved description of bit e ? added ordering information ( section 3.1 ) ? updated store and transport requirements ( ta b l e 1 9 ) ? adjusted v lu value ( table 19 ) ? enhanced description about cascading ( section 14.1 ) ? added section 17 ? fixed typos pcf85134 v.2 20110725 product data sheet - pcf85134_1 pcf85134_1 20091217 product data sheet - - pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 49 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 23. legal information 23.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 23.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 23.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 50 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 23.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp semiconductors n.v. 24. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 51 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 25. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 2. ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 4. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 5. selection of possible display configurations . . . .6 table 6. biasing characteristics . . . . . . . . . . . . . . . . . . . .8 table 7. lcd frame frequencies . . . . . . . . . . . . . . . . . .16 table 8. standard ram filling in 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 9. entire ram filling by rewriting in 1:3 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 10. blink frequencies . . . . . . . . . . . . . . . . . . . . . . .22 table 11. definition of commands . . . . . . . . . . . . . . . . . .22 table 12. mode-set command bit description . . . . . . . . .23 table 13. load-data-pointer command bit description . .23 table 14. device-select command bit description . . . . . .23 table 15. bank-select command bit description . . . . . . . .24 table 16. blink-select command bit description . . . . . . .24 table 17. i 2 c slave address byte . . . . . . . . . . . . . . . . . . .27 table 18. control byte description . . . . . . . . . . . . . . . . . .28 table 19. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .31 table 20. static characteristics . . . . . . . . . . . . . . . . . . . .32 table 21. dynamic characteristics . . . . . . . . . . . . . . . . . .34 table 22. addressing cascaded pcf85134 . . . . . . . . . .37 table 23. sync contact resistance . . . . . . . . . . . . . . . . .39 table 24. snpb eutectic process (from j-std-020d) . . .43 table 25. lead-free process (from j-std-020d) . . . . . .43 table 26. selection of lcd segment drivers . . . . . . . . . .45 table 27. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 28. revision history . . . . . . . . . . . . . . . . . . . . . . . .48 pcf85134 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights re served. product data sheet rev. 3 ? 12 may 2014 52 of 53 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates 26. figures fig 1. block diagram of pcf85134 . . . . . . . . . . . . . . . . .3 fig 2. pin configuration for sot315-1 (pcf85134). . . . .4 fig 3. example of displays suitable for pcf85134 . . . . .6 fig 4. typical system configuration . . . . . . . . . . . . . . . . .7 fig 5. electro-optical ch aracteristic: relative transmission curve of the liquid . . . . . . . . . . . . . .10 fig 6. static drive mode waveforms . . . . . . . . . . . . . . . . 11 fig 7. waveforms for the 1:2 multiplex drive mode with 1 2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 fig 8. waveforms for the 1:2 multiplex drive mode with 1 3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 fig 9. waveforms for the 1:3 multiplex drive mode with 1 3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 fig 10. waveforms for the 1:4 multiplex drive mode with 1 3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 fig 11. display ram bit map . . . . . . . . . . . . . . . . . . . . . .17 fig 12. relationship between lcd layout, drive mode, display ram filling order and display data transmitted over the i 2 c-bus . . . . . . . . . . . . . . . .18 fig 13. bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 fig 14. definition of start and stop conditions. . . . . .25 fig 15. system configuration . . . . . . . . . . . . . . . . . . . . . .26 fig 16. acknowledgement of the i 2 c-bus . . . . . . . . . . . .26 fig 17. i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .28 fig 18. control byte format . . . . . . . . . . . . . . . . . . . . . . .28 fig 19. device protection diagram . . . . . . . . . . . . . . . . . .29 fig 20. driver timing waveforms . . . . . . . . . . . . . . . . . . .35 fig 21. i 2 c-bus timing waveforms . . . . . . . . . . . . . . . . . .36 fig 22. cascaded pcf85134 configuration . . . . . . . . . . .38 fig 23. synchronization of the cascade for various pcf85134 drive modes . . . . . . . . . . . . . . . . . . . .39 fig 24. package outline sot315-1 (lqfp80) . . . . . . . . .41 fig 25. temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 nxp semiconductors pcf85134 universal 60 x 4 lcd segment driver for low multiplex rates ? nxp semiconductors n.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 12 may 2014 document identifier: pcf85134 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 27. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 power-on reset (por) . . . . . . . . . . . . . . . . . . 7 7.2 lcd bias generator . . . . . . . . . . . . . . . . . . . . . 7 7.3 lcd voltage selector . . . . . . . . . . . . . . . . . . . . 8 7.3.1 electro-optical performance . . . . . . . . . . . . . . . 9 7.4 lcd drive mode waveforms . . . . . . . . . . . . . . 11 7.4.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . 11 7.4.2 1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 12 7.4.3 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 14 7.4.4 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 15 7.5 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5.1 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6 timing and frame frequency . . . . . . . . . . . . . . 16 7.7 display register . . . . . . . . . . . . . . . . . . . . . . . . 16 7.8 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16 7.9 backplane outputs . . . . . . . . . . . . . . . . . . . . . 17 7.10 display ram . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.10.1 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.10.2 subaddress counter . . . . . . . . . . . . . . . . . . . . 19 7.10.3 ram writing in 1:3 multiplex drive mode. . . . . 20 7.10.4 bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.10.4.1 output bank selector . . . . . . . . . . . . . . . . . . . 21 7.10.4.2 input bank selector . . . . . . . . . . . . . . . . . . . . . 21 7.11 blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.12 command decoder . . . . . . . . . . . . . . . . . . . . . 22 7.13 display controller . . . . . . . . . . . . . . . . . . . . . . 24 8 characteristics of the i 2 c-bus . . . . . . . . . . . . 25 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1.1 start and stop conditions . . . . . . . . . . . . . 25 8.2 system configuration . . . . . . . . . . . . . . . . . . . 25 8.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.4 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 27 8.5 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.6 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 27 9 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 29 10 safety notes . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31 12 static characteristics . . . . . . . . . . . . . . . . . . . 32 13 dynamic characteristics. . . . . . . . . . . . . . . . . 34 14 application information . . . . . . . . . . . . . . . . . 37 14.1 cascaded operation. . . . . . . . . . . . . . . . . . . . 37 15 package outline. . . . . . . . . . . . . . . . . . . . . . . . 41 16 handling information . . . . . . . . . . . . . . . . . . . 42 17 packing information . . . . . . . . . . . . . . . . . . . . 42 18 soldering of smd packages . . . . . . . . . . . . . . 42 18.1 introduction to soldering. . . . . . . . . . . . . . . . . 42 18.2 wave and reflow soldering. . . . . . . . . . . . . . . 42 18.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 43 18.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 43 19 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 19.1 lcd segment driver selection . . . . . . . . . . . . 45 20 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 47 21 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 22 revision history . . . . . . . . . . . . . . . . . . . . . . . 48 23 legal information . . . . . . . . . . . . . . . . . . . . . . 49 23.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 49 23.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 23.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 49 23.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 50 24 contact information . . . . . . . . . . . . . . . . . . . . 50 25 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 26 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 27 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 |
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